Witnessing the advancing scale and complexity of chip design and benefiting from high-performance computation technologies, the simulation of Very Large Scale Integration (VLSI) Circuits imposes an increasing requirement for acceleration through parallel computing with GPU devices. However, the conventional parallel strategies do not fully align with modern GPU abilities, leading to new challenges in the parallelism of VLSI simulation when using GPU, despite some previous successful demonstrations of significant acceleration. In this paper, we propose a novel approach to accelerate 4-value logic timing-aware gate-level logic simulation using waveform-based GPU parallelism. Our approach utilizes a new strategy that can effectively handle the dependency between tasks during the parallelism, reducing the synchronization requirement between CPU and GPU when parallelizing the simulation on combinational circuits. This approach requires only one round of data transfer and hence achieves one-pass parallelism. Moreover, to overcome the difficulty within the adoption of our strategy in GPU devices, we design a series of data structures and tune them to dynamically allocate and store new-generated output with uncertain scale. Finally, experiments are carried out on industrial-scale open-source benchmarks to demonstrate the performance gain of our approach compared to several state-of-the-art baselines.

翻译：随着芯片设计规模和复杂度的不断提升，并受益于高性能计算技术的发展，超大规模集成电路(VLSI)的仿真对通过GPU设备并行计算实现加速的需求日益增长。然而，尽管先前已有通过GPU实现显著加速的成功案例，传统并行策略与现代GPU能力并不完全匹配，这给基于GPU的VLSI仿真并行化带来了新的挑战。本文提出了一种新颖方法，利用基于波形驱动的GPU并行性来加速4值逻辑的时序感知门级逻辑仿真。该方法采用一种新策略，可在并行过程中有效处理任务间的依赖关系，从而在组合电路的仿真并行化中减少CPU与GPU间的同步需求。该策略仅需一次数据传输即可实现单遍并行。此外，为克服该策略在GPU设备中应用的难点，我们设计了一系列数据结构并对其进行调优，以动态分配和存储规模不确定的新生成输出。最后，基于工业级开源基准测试的实验结果表明，与多个最先进基线方法相比，本方法在性能上具有显著优势。