As the demand for high-speed and low-power electronics continues to grow, the quasi-delay-insensitive (QDI) asynchronous domain of digital design has emerged as a promising alternative to traditional clock-based designs. However, the adoption of the paradigm has been greatly limited due to the lack of mature computer-aided design (CAD) tools and a substantially larger area footprint, owing to various architectural constraints. Monolithic-3D (M3D) technology has recently paved the way for manufacturing highly dense integrated circuits (ICs) through sequential integration, resulting in a reduced area footprint, shorter wirelengths, and increased performance. In this study, we integrate M3D technology with QDI Null Convention Logic (NCL) and propose a design methodology for the implementation of M3D-based NCL standard cells, aimed at mitigating the area inefficiencies of traditional planar or 2D counterparts. Furthermore, we employed the threshold gates to design an M3D-NCL unsigned array multiplier circuit. Simulation results suggest that, for a conservative wirelength reduction resulting from M3D implementation, a substantial area reduction of 44% can be achieved while simultaneously reducing delay and power by approximately 31% and 17%, respectively.

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