Dynamic digital timing analysis aims at substituting highly accurate but slow analog simulations of digital circuits with less accurate but fast digital approaches to facilitate tracing timing relations between individual transitions in a signal trace. This primarily requires gate delay models, where the input-to-output delay of a transition also depends on the signal history. We focus on a recently proposed hybrid delay model for CMOS multi-input gates, exemplified by a 2-input \NOR\ gate, which is the only delay model known to us that faithfully captures both single-input switching (SIS) and multi-input switching (MIS) effects, also known as ``Charlie effects''. Despite its simplicity as a first-order model, simulations have revealed that suitably parametrized versions of the model predict the actual delays of NOR gates accurately. However, the approach considers isolated gates without their interconnect. In this work, we augment the existing model and its theoretical analysis by a first-order interconnect, and conduct a systematic evaluation of the resulting modeling accuracy: Using SPICE simulations, we study both SIS and MIS effects on the overall delay of \NOR\ gates under variation of input driving strength, wire length, load capacitance and CMOS technology, and compare it to the predictions of appropriately parametrized versions of our model. Overall, our results reveal a surprisingly good accuracy of our fast delay model.

翻译：动态数字时序分析旨在用精度较低但速度较快的数字方法替代高精度但缓慢的数字电路模拟仿真，以追踪信号迹中单个跃迁之间的时序关系。这主要依赖于门延迟模型，其中跃迁的输入到输出延迟还取决于信号历史。我们重点关注近期提出的一种针对CMOS多输入门的混合延迟模型，以二输入或非门为例，这是目前已知唯一能同时忠实捕获单输入切换和多输入切换效应（即“查理效应”）的延迟模型。尽管作为一阶模型具有简洁性，但仿真表明，适当参数化的模型版本能准确预测或非门的实际延迟。然而，该模型仅考虑孤立门电路而忽略了互连结构。在本工作中，我们通过一阶互连模型扩展了现有模型及其理论分析，并对由此产生的建模精度进行了系统评估：利用SPICE仿真，我们研究了输入驱动强度、导线长度、负载电容和CMOS工艺变化下或非门总延迟中的单输入切换与多输入切换效应，并将其与适当参数化的模型预测结果进行比较。总体而言，我们的结果表明该快速延迟模型具有出人意料的良好精度。