Intellectual Property (IP) piracy, overbuilding, reverse engineering, and hardware Trojan are serious security concerns during integrated circuit (IC) development. Logic locking has proven to be a solid defence for mitigating these threats. The existing logic locking techniques are vulnerable to SAT-based attacks. However, several SAT-resistant logic locking methods are reported; they require significant overhead. This paper proposes a novel input dependent key-based logic locking (IDKLL) that effectively prevents SAT-based attacks with low overhead. We first introduce a novel idea of IDKLL, where a design is locked such that it functions correctly for all input patterns only when their corresponding valid key sequences are applied. In contrast to conventional logic locking, the proposed IDKLL method uses multiple key sequences (instead of a single key sequence) as a valid key that provides correct functionality for all inputs. Further, we propose a sub-circuit replacement based IDKLL approach called SubLock that locks the design by replacing the original sub-circuitry with the corresponding IDKLL based locked circuit to prevent SAT attack with low overhead. The experimental evaluation on ISCAS benchmarks shows that the proposed SubLock mitigates the SAT attack with high security and reduced overhead over the well-known existing methods.

翻译：在集成电路开发过程中，知识产权盗用、过量生产、逆向工程和硬件木马是严重的安全隐患。逻辑锁定已被证明是缓解这些威胁的有效防御手段。现有逻辑锁定技术易受基于SAT的攻击。尽管已报道多种抗SAT的逻辑锁定方法，但其开销显著。本文提出了一种新颖的输入相关密钥逻辑锁定方法，能以较低开销有效抵御SAT攻击。我们首先阐述IDKLL的核心思想：通过锁定设计，使得仅当输入模式对应的有效密钥序列被施加时，电路才能对所有输入模式实现正确功能。与传统逻辑锁定使用单一密钥序列不同，所提出的IDKLL方法采用多组密钥序列作为有效密钥，为所有输入提供正确功能。进一步，我们提出基于子电路替换的IDKLL方案SubLock，通过将原子电路替换为对应的IDKLL锁定电路来实现设计锁定，在低开销条件下有效防御SAT攻击。基于ISCAS基准电路的实验评估表明，相较于现有主流方法，SubLock能以更高安全性和更低开销实现SAT攻击防护。