Thermodynamic computing lets stochastic physical dynamics carry out a computation and reads out the result as a time average. Recently, thermodynamic computing has been demonstrated on several hardware platforms, including digital CMOS circuits based on stochastic computing. Superconducting single-flux-quantum (SFQ) logic offers very high clock rates and very low switching energy, but it heavily penalizes state, memory, fan-out, and feedback, i.e., exactly the per-neuron accumulators on which such designs rely. We therefore realize thermodynamic computing in SFQ logic through a co-design of a generative model and its circuit in which the datapath holds no state at all. The model is a class-conditional flow-matching image generator, which transforms Gaussian noise into an image of the requested class along a short, deterministic path of four Euler steps; in hardware, these steps are unrolled into a feed-forward pipeline of stochastic bitstream operators, whose output is read out as a time average, as in thermodynamic computing, without any relaxation phase. Each layer of the model is a butterfly-factorized linear map built exclusively from multiplexers that operate on split-unipolar bitstreams. The ReLU activation, which in stochastic computing requires a per-neuron up/down counter (accounting for 60-70% of the JJs in a counter-based design), is replaced by a stateless AND-NOT gate whose one-clock input skew is provided at no cost by SFQ gate-level pipelining. The models are trained directly on the stream representation of the hardware, with a regularizer that bounds the stream gains. Synthesis with an SFQ design flow shows that stochastic streams tolerate relaxed path balancing, which reduces the Josephson-junction (JJ) count of a hard-wired stage by 40-47%.

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