In order to mitigate the security threat of quantum computers, NIST is undertaking a process to standardize post-quantum cryptosystems, aiming to assess their security and speed up their adoption in production scenarios. Several hardware and software implementations have been proposed for each candidate, while only a few target heterogeneous platforms featuring CPUs and FPGAs. This work presents a HW/SW co-design of BIKE for embedded platforms featuring both CPUs and small FPGAs and employs high-level synthesis (HLS) to timely deliver the hardware accelerators. In contrast to state-of-the-art solutions targeting performance-optimized HLS accelerators, the proposed solution targets the small FPGAs implemented in the heterogeneous platforms for embedded systems. Compared to the software-only execution of BIKE, the experimental results collected on the systems-on-chip of the entire Xilinx Zynq-7000 family highlight a performance speedup ranging from 1.37x, on Z-7010, to 2.78x, on Z-7020.

翻译：为了减轻量子计算机的安全威胁,NIST正在开展一个进程,使量子加密后系统标准化,目的是评估其安全性并加快其在生产情景中的采用速度,为每个候选人提出了若干硬件和软件实施建议,而只有几个以CPU和FPGA为主的目标不同平台。这项工作为由CPU和小FPGA组成的嵌入式平台共同设计了HW/SW BIKE, 并使用高级合成器及时交付硬件加速器。与针对性能优化HLS加速器的最先进的解决方案相比,拟议解决方案针对的是嵌入系统多式平台中执行的小型FPGA。与仅软件执行Xilinx Zynq-7000整个Xilinx Zynq-7000家庭在系统-芯片上收集的实验结果相比,其性能加速度从Z-7010的1.37x到Z-7020的2.78x不等。