As the size of real-world graphs increases, training Graph Neural Networks (GNNs) has become time-consuming and requires acceleration. While previous works have demonstrated the potential of utilizing FPGA for accelerating GNN training, few works have been carried out to accelerate GNN training with multiple FPGAs due to the necessity of hardware expertise and substantial development effort. To this end, we propose HitGNN, a framework that enables users to effortlessly map GNN training workloads onto a CPU-Multi-FPGA platform for acceleration. In particular, HitGNN takes the user-defined synchronous GNN training algorithm, GNN model, and platform metadata as input, determines the design parameters based on the platform metadata, and performs hardware mapping onto the CPU+Multi-FPGA platform, automatically. HitGNN consists of the following building blocks: (1) high-level application programming interfaces (APIs) that allow users to specify various synchronous GNN training algorithms and GNN models with only a handful of lines of code; (2) a software generator that generates a host program that performs mini-batch sampling, manages CPU-FPGA communication, and handles workload balancing among the FPGAs; (3) an accelerator generator that generates GNN kernels with optimized datapath and memory organization. We show that existing synchronous GNN training algorithms such as DistDGL and PaGraph can be easily deployed on a CPU+Multi-FPGA platform using our framework, while achieving high training throughput. Compared with the state-of-the-art frameworks that accelerate synchronous GNN training on a multi-GPU platform, HitGNN achieves up to 27.21x bandwidth efficiency, and up to 4.26x speedup using much less compute power and memory bandwidth than GPUs. In addition, HitGNN demonstrates good scalability to 16 FPGAs on a CPU+Multi-FPGA platform.

翻译：随着实际图数据规模的增大，训练图神经网络已成为耗时任务并亟需加速技术。尽管已有研究展示了利用FPGA加速GNN训练的潜力，但由于需要硬件专业知识及大量开发工作，目前鲜有工作实现多FPGA加速GNN训练。为此，我们提出HitGNN框架，该框架使研究人员能够轻松地将GNN训练工作负载映射到CPU-多FPGA平台实现加速。具体而言，HitGNN以用户定义的同步GNN训练算法、GNN模型及平台元数据为输入，基于平台元数据自动确定设计参数并执行到CPU+多FPGA平台的硬件映射。该框架包含以下核心模块：（1）高级应用程序接口，允许用户仅用少量代码定义各类同步GNN训练算法与GNN模型；（2）软件生成器，生成执行小批量采样、管理CPU-FPGA通信及处理FPGA间工作负载均衡的主机程序；（3）加速器生成器，生成具有优化数据通路与存储结构的GNN核函数。实验表明，DistDGL与PaGraph等同步GNN训练算法可通过本框架便捷部署于CPU+多FPGA平台，并实现高训练吞吐量。与在多GPU平台上加速同步GNN训练的现有最优框架相比，HitGNN的带宽效率最高提升27.21倍，在远低于GPU的计算能力与内存带宽条件下实现最高4.26倍加速比。此外，HitGNN在CPU+多FPGA平台上展现出对16块FPGA的良好可扩展性。