To increase the science rate for high data rates/volumes, Thomas Jefferson National Accelerator Facility (JLab) has partnered with Energy Sciences Network (ESnet) to define an edge to data center traffic shaping / steering transport capability featuring data event-aware network shaping and forwarding. The keystone of this ESnet JLab FPGA Accelerated Transport (EJFAT) is the joint development of a dynamic compute work Load Balancer (LB) of UDP streamed data. The LB is a suite consisting of a Field Programmable Gate Array (FPGA) executing the dynamically configurable, low fixed latency LB data plane featuring real-time packet redirection at high throughput, and a control plane running on the FPGA host computer that monitors network and compute farm telemetry in order to make dynamic decisions for destination compute host redirection / load balancing.

翻译：为提升高数据速率/容量下的科研产出效率，托马斯·杰斐逊国家加速器实验室（JLab）与能源科学网络（ESnet）合作，定义了一种面向边缘到数据中心流量整形/引导的传输能力，该能力具备数据事件感知的网络整形与转发功能。这一ESnet-JLab FPGA加速传输（EJFAT）框架的核心在于联合开发针对UDP流数据的动态计算负载均衡器（LB）。该负载均衡器由以下组件构成：部署于现场可编程门阵列（FPGA）上的数据平面，其具备动态可配置、低固定延迟特性，通过高速实时数据包重定向实现高效转发；以及运行于FPGA宿主机上的控制平面，通过监测网络与计算集群遥测数据，动态决策目标计算主机的重定向/负载均衡策略。