Designing field-programmable gate array (FPGA)-based accelerators for modern artificial intelligence workloads requires navigating a large and complex hardware design space encompassing architectural parameters, dataflow strategies, and memory hierarchies, making the process time-consuming and resource-intensive. While the SECDA methodology enables rapid hardware-software co-design of accelerators through SystemC simulation and FPGA execution, identifying optimal accelerator configurations still requires substantial manual effort and domain expertise. This work presents SECDA-DSE, a framework that integrates Large Language Models (LLMs) into the SECDA ecosystem, comprising tools built around SECDA to automate the design space exploration (DSE) of FPGA-based accelerators. SECDA-DSE combines a structured DSE Explorer for generating accelerator configurations with an LLM Stack that performs reasoning-guided exploration using retrieval-augmented generation and chain-of-thought prompting, alongside a feedback loop that enables reinforced fine-tuning for continuous improvement. We demonstrate the feasibility of SECDA-DSE through an initial high-level synthesis based evaluation of a generated accelerator design that meets synthesis timing and resource constraints on an Zynq-7000 FPGA.

翻译：为现代人工智能工作负载设计基于现场可编程门阵列（FPGA）的加速器，需要探索涵盖架构参数、数据流策略和存储层次结构在内的大型复杂硬件设计空间，这一过程耗时且资源密集。尽管SECDA方法通过SystemC仿真和FPGA执行实现了加速器的快速软硬件协同设计，但确定最优加速器配置仍需大量手动工作和领域专业知识。本文提出SECDA-DSE框架，该框架将大语言模型（LLM）集成到SECDA生态系统，围绕SECDA构建工具套件实现FPGA加速器设计空间探索（DSE）的自动化。SECDA-DSE结合了用于生成加速器配置的结构化DSE探索器，以及基于检索增强生成和思维链提示执行推理引导探索的LLM栈，并配备反馈回路实现强化微调以持续改进。我们通过初步的高层综合评估验证了SECDA-DSE的可行性，在Zynq-7000 FPGA上生成的加速器设计满足综合时序和资源约束。