Recent advances in large language models (LLMs) have enabled the automatic synthesis (generation) of register-transfer level (RTL) code from natural language instructions, offering a promising pathway to accelerate chip design. Unlike typical natural language (and software coding) tasks, LLM-based RTL code generation demands strict cycle accuracy with concurrency, where minor logical errors can render a circuit unusable or insecure. While prior work has explored hallucination mitigation via external verification, self-evaluation prompts, retrieval-augmented prompting, domain specific fine-tuning, agentic solutions, and reasoning, these approaches largely overlook the attention-oriented internal mechanisms of LLMs that may inherently correlate with RTL correctness. This work proposes CASS-RTL, a first-of-its-kind framework for discovering and leveraging LLMs' correctness-aware components to guide RTL generation toward functionally accurate outputs. We (i) identify attention heads whose activation patterns consistently differentiate correct from incorrect RTL; (ii) construct a low-dimensional subspace capturing correctness-relevant signals; and (iii) design a lightweight, geometry-aware intervention that steers the model at inference time. CASS-RTL is fully model-agnostic, requires no additional supervision or retraining, and readily integrates into existing models. Empirically, we evaluate CASS-RTL on multiple models and observe 10%-20% improvement in pass@1/5/10 accuracy on VerilogEval and 5% improvement on CVDP, demonstrating the effectiveness of our method in enhancing reliability without sacrificing model efficiency or requiring a large labeled dataset for fine-tuning.

翻译：最新的大语言模型进展使得从自然语言指令自动综合（生成）寄存器传输级代码成为可能，为加速芯片设计提供了一条前景广阔的路径。与典型的自然语言（及软件编码）任务不同，基于大语言模型的RTL代码生成要求严格的周期精度与并发性，即便是微小的逻辑错误都可能导致电路无法使用或存在安全隐患。虽然先前的研究已探索通过外部验证、自我评估提示、检索增强提示、领域特定微调、智能体解决方案及推理机制来缓解幻觉现象，但这些方法大都忽略了大语言模型中与RTL正确性存在内在关联的注意力导向内部机制。本文提出CASS-RTL——首个用于发现并利用大语言模型中正确性感知组件以引导RTL生成朝向功能准确输出的框架。我们：①识别出激活模式能持续区分正确与错误RTL的注意力头部；②构建一个捕捉正确性相关信号的低维子空间；③设计一种轻量级的几何感知干预方法，在推理阶段对模型进行导向。CASS-RTL完全与模型无关，无需额外监督或重训练，可轻松集成至现有模型。通过在多款模型上的实验评估，我们在VerilogEval上观察到pass@1/5/10准确率提升10%-20%，在CVDP上提升5%，充分证明该方法在不牺牲模型效率或需要大规模标注数据集微调的前提下，有效增强了RTL生成的可靠性。