Various studies have shown the advantages of using Machine Learning (ML) techniques for analog and digital IC design automation and optimization. Data scarcity is still an issue for electronic designs, while training highly accurate ML models. This work proposes generating and evaluating artificial data using generative adversarial networks (GANs) for circuit data to aid and improve the accuracy of ML models trained with a small training data set. The training data is obtained by various simulations in the Cadence Virtuoso, HSPICE, and Microcap design environment with TSMC 180nm and 22nm CMOS technology nodes. The artificial data is generated and tested for an appropriate set of analog and digital circuits. The experimental results show that the proposed artificial data generation significantly improves ML models and reduces the percentage error by more than 50\% of the original percentage error, which were previously trained with insufficient data. Furthermore, this research aims to contribute to the extensive application of AI/ML in the field of VLSI design and technology by relieving the training data availability-related challenges.

翻译：多项研究已表明，在模拟与数字集成电路设计自动化及优化过程中应用机器学习技术具有显著优势。然而，在训练高精度机器学习模型时，电子设计领域仍面临数据稀缺问题。本研究提出采用生成对抗网络（GANs）生成并评估电路人工数据，以辅助并提升基于小样本训练数据集的机器学习模型精度。训练数据通过Cadence Virtuoso、HSPICE及Microcap设计环境，采用台积电180nm与22nm CMOS工艺节点进行多类仿真获取。人工数据针对模拟与数字电路的典型组合进行生成与验证。实验结果表明，所提出的人工数据生成方法显著提升了机器学习模型性能，使原本因数据不足导致的原始百分比误差降低超过50%。此外，本研究通过缓解训练数据可用性方面的挑战，旨在推动人工智能/机器学习技术在超大规模集成电路设计与工艺领域的广泛应用。