The advent of large, high-density FPGAs such as the AMD Versal enables efficient hardware implementation of neuromorphic Ising machines, unlocking unprecedented performance for complex combinatorial optimizations. A critical application for this computing paradigm is dynamic powergrid optimization, specifically Distribution Network Reconfiguration (DNR), which seeks to mitigate severe resistive losses and reduce electricity costs by optimizing network switch configurations in real time. This paper presents an FPGA-based neuromorphic higher-order Ising machine for high-speed, adaptive DNR. By directly mapping DNR onto higher-order Ising interactions via a polynomial unconstrained binary optimization (PUBO) formulation, the proposed architecture requires only 179 spins for the IEEE 33-bus network, which represents a 6 times reduction compared to standard quadratic formulations. Implemented on an AMD Versal Premium VP1802 FPGA, the architecture executes parallel spin-group updates every 20 ns and solves 33-, 51-, and 69-bus benchmark networks with median latencies of 1.6-29.3 ms, yielding a 7-58 times speedup over Gurobi to the first optimal solution. Using the solver with expanded network-switching flexibility reduces power loss by 80.71 kW (57.83%), while adaptive reconfiguration every 10 s under time-varying demand saves 131.16 kWh/day over static daily reconfiguration, highlighting the potential of higher-order Ising hardware for fast, adaptive smart grid management.

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