Achieving timing closure in FPGA designs is crucial, especially for high-performance applications. The Vivado Design Suite offers several strategies for optimization, but finding the best configuration for a given project remains challenging. This paper explores the various Vivado's timing directives and strategies to improve performance across timing, area, and runtime. Through two test-case designs, an NQR spectrometer SoC-FPGA and a digital readout ASIC prototype for high energy physics particle detector's, different strategies and configurations are compared to identify the most efficient flow.

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