The increasing complexity and demand for faster, energy-efficient hardware designs necessitate innovative High-Level Synthesis (HLS) methodologies. This paper explores the potential of Large Language Models (LLMs) to streamline or replace the HLS process, leveraging their ability to understand natural language specifications and refactor code. We survey the current research and conduct experiments comparing Verilog designs generated by a standard HLS tool (Vitis HLS) with those produced by LLMs translating C code or natural language specifications. Our evaluation focuses on quantifying the impact on performance, power, and resource utilization, providing an assessment of the efficiency of LLM-based approaches. This study aims to illuminate the role of LLMs in HLS, identifying promising directions for optimized hardware design in applications such as AI acceleration, embedded systems, and high-performance computing.

翻译：日益增长的硬件设计复杂性和对更快、更节能设计的需求，催生了创新的高层次综合（HLS）方法。本文探讨了大型语言模型（LLMs）在简化或替代HLS流程方面的潜力，利用其理解自然语言规格说明和重构代码的能力。我们综述了当前的研究，并通过实验比较了标准HLS工具（Vitis HLS）生成的Verilog设计与LLMs翻译C代码或自然语言规格说明所产生的设计。我们的评估重点在于量化其对性能、功耗和资源利用率的影响，从而对基于LLM的方法的效率进行评估。本研究旨在阐明LLMs在HLS中的作用，为人工智能加速、嵌入式系统和高性能计算等应用中的优化硬件设计指明有前景的方向。