CXL (Compute Express Link) is an emerging open industry-standard interconnect between processing and memory devices that is expected to revolutionize the way systems are designed. It enables cache-coherent, shared memory pools in a disaggregated fashion at unprecedented scales, allowing algorithms to interact with various storage devices using simple loads and stores. While CXL unleashes unique opportunities, it also introduces challenges of data management and crash consistency. For example, CXL currently lacks an adequate programming model, making it impossible to reason about the correctness and behavior of systems on top. In this work, we present CXL0, the first programming model for concurrent programs over CXL. We propose a high-level abstraction for memory accesses and formally define operational semantics. We demonstrate that CXL0 captures a wide range of current and future CXL setups and perform initial measurements on real hardware. To illustrate the usefulness of CXL0, we present a general transformation that enhances any linearizable concurrent algorithm with durability in a distributed partial-crash setting. We believe that this work will serve as a stepping stone for systems design and programming on top of CXL.

翻译：CXL（Compute Express Link）是一种新兴的开放行业标准互连技术，用于连接处理器与内存设备，有望彻底改变系统设计方式。它以分解式架构在空前规模上实现缓存一致性的共享内存池，使得算法能够通过简单的加载和存储操作与各类存储设备交互。尽管CXL带来了独特机遇，但也引入了数据管理与故障一致性的挑战。例如，当前CXL缺乏完善的编程模型，导致无法在理论上保证上层系统的正确性与行为可推演性。本研究提出CXL0——首个面向CXL并发程序的编程模型。我们建立了内存访问的高层抽象形式化定义操作语义，论证了CXL0能够涵盖当前及未来多种CXL配置方案，并在真实硬件上进行了初步测量。为展示CXL0的实用性，我们提出一种通用转换机制，可在分布式部分故障场景中为任意线性化并发算法增强持久性保障。我们相信这项工作将为基于CXL的系统设计与编程奠定基石。