Multi-core vector processor architectures excel in handling computationally intensive vectorizable tasks but struggle to achieve optimal resource utilization when facing sequential and control tasks that cannot be vectorized. This work presents Spatzformer, the first reconfigurable RISC-V V (RVV) architecture developed from a baseline open-source dual-core cluster based on Snitch scalar cores augmented with compact Spatz vector units. Spatzformer operates in two distinct modes: split mode, working as a dual-core vector architecture to handle vectorizable tasks concurrently, and merge mode, where two vector units are driven by a single scalar core, allowing the remaining scalar core to handle non-vectorizable control tasks. We implement Spatzformer in a 12-nm technology node and characterize the cost of the added architectural reconfigurability. We show that merge mode accelerates mixed scalar-vector kernels by up to 1.8x compared to split mode. Moreover, it accelerates the vector kernels that require fine-grained synchronization (such as FFT) by up to 20% with respect to the baseline. The reconfigurability features do not degrade the architecture's maximum frequency (1.2GHz, TT, 0.8V, 25C) and have a negligible area impact (+1.4%), with a worst-case energy efficiency drop of only 7% with respect to the non-reconfigurable baseline.

翻译：多核向量处理器架构在处理可向量化的计算密集型任务时表现出色，但在面对无法向量化的顺序和控制任务时难以实现最优资源利用率。本文提出Spatzformer，这是首个基于开源双核集群（以Snitch标量核为基础，通过紧凑型Spatz向量单元增强）开发的可重构RISC-V V（RVV）架构。Spatzformer具有两种独立工作模式：拆分模式下作为双核向量架构并行处理可向量化任务；合并模式下两个向量单元由单个标量核驱动，剩余标量核可专门处理不可向量化的控制任务。我们在12纳米工艺节点上实现了Spatzformer，并量化了架构可重构性带来的成本。实验表明：相较于拆分模式，合并模式对混合标量-向量内核的加速比最高可达1.8倍；对于需要细粒度同步的向量内核（如FFT），较基线架构最高可加速20%。可重构特性未降低架构的最高工作频率（1.2GHz，TT，0.8V，25℃），面积开销可忽略（+1.4%），在最坏情况下能效仅比不可重构基线下降7%。