Hybrid High-performance Computing (HPC)-quantum workloads based on circuit cutting decompose large quantum circuits into independent fragments, but existing frameworks tightly couple cutting logic to execution orchestration, preventing HPC centers from applying mature resource management policies to Noisy Intermediate-Scale Quantum (NISQ) workloads. We present DQR (Dynamic Queue Router), a runtime framework that bridges this gap by treating circuit fragments as first-class schedulable units. The framework introduces a backend-agnostic fragment descriptor to expose structural properties without requiring execution layers to parse quantum code, a wave-based coordinator that achieves pipeline concurrency via non-blocking polling, and a production-ready implementation on the CESGA Qmio supercomputer integrating both QPUs local on-premises (Qmio) and remote cloud (IBM Torino) backends. Experiments on a 32-qubit Hardware-Efficient Ansatz (HEA) circuit demonstrate not only makespan improvements over a monolithic CPU baseline but also transparent per-fragment failover recovery-specifically rerouting tasks from the local QPU to classical simulators upon encountering hardware-level incompatibilities-without pipeline restart. For deeper circuits, the coordination residual accounts for only 5% of the total execution time, highlighting the framework's scalability. These results show that DQR enables HPC centers to integrate NISQ workloads into existing production infrastructure while preserving the flexibility to adopt improved cutting algorithms or heterogeneous backend technologies.

翻译：面向混合高性能计算-量子工作负载的电路切分技术，将大规模量子电路分解为独立片段，但现有框架将切分逻辑与执行编排紧密耦合，阻碍了HPC中心将成熟资源管理策略应用于含噪中等规模量子（NISQ）工作负载。本文提出DQR（动态队列路由器）运行时框架，通过将电路片段视为一级可调度单元来弥合这一鸿沟。该框架引入后端无关的片段描述符，无需执行层解析量子代码即可暴露结构属性；提出基于波的协调器，通过非阻塞轮询实现流水线并发；并在集成本地QPU（Qmio）与远程云端（IBM Torino）后端的CESGA Qmio超算上实现生产级部署。在32量子比特硬件高效拟设（HEA）电路上的实验表明，该方案不仅较单核CPU基线缩短完工时间，还能实现透明的逐片段故障切换恢复——当检测到硬件级不兼容时，自动将任务从本地QPU重路由至经典模拟器，且无需重启流水线。对于更深层电路，协调开销仅占总执行时间的5%，彰显了框架的可扩展性。这些结果表明，DQR使HPC中心能够将NISQ工作负载集成到现有生产基础设施中，同时保留采用改进切分算法或异构后端技术的灵活性。