In many modern AI chips and multicore systems-on-chip, embedded applications exhibit predictable inter-core traffic behavior that can be characterized at design time. For such applications, a variety of design-time traffic management and network optimization techniques can be employed to improve NoC power and performance. To exploit this predictability, we propose a novel low-power circuit-switched NoC design. It uses the Spatial Division Multiplexing (SDM) technique to establish circuits, implemented as subsets of NoC wires, for the communication flows of a target application. To further reduce the power profile of SDM, the design incorporates a new router architecture that combines hard-wired switches with conventional programmable crossbars. The architecture is complemented by an algorithm that maps application tasks onto a mesh NoC and assigns an SDM route with adequate bit-width to each circuit built for inter-task communication flows. Compared with a conventional packet-switched NoC, the proposed approach achieves approximately 38% lower NoC power consumption, 19% smaller area, and 12% lower packet latency.

翻译：在现代许多AI芯片和多核片上系统中，嵌入式应用呈现出可在设计阶段表征的可预测核间通信行为。针对此类应用，可采用多种设计时流量管理与网络优化技术来提升NoC功耗与性能。为利用这种可预测性，我们提出一种新型低功耗电路交换NoC架构。该架构采用空分复用技术建立电路，通过为特定应用的通信流分配NoC线路子集实现电路构建。为进一步降低SDM功耗，该设计融合了新型路由器架构，将硬连线开关与传统可编程交叉开关相结合。配套算法将应用任务映射至网格状NoC，并为核间通信流构建的每条电路分配具有适当位宽的SDM路由。与传统分组交换NoC相比，所提方案可实现约38%的NoC功耗降低、19%的面积缩减以及12%的数据包延迟改善。