This paper introduces a search algorithm for index structures based on a B+ tree, specifically optimized for execution on a field-programmable gate array (FPGA). Our implementation efficiently traverses and reuses tree nodes by processing a batch of search keys level by level. This approach reduces costly global memory accesses, improves reuse of loaded B+ tree nodes, and enables parallel search key comparisons directly on the FPGA. Using a high-level synthesis (HLS) approach, we developed a highly flexible and configurable search kernel design supporting variable batch sizes, customizable node sizes, and arbitrary tree depths. The final design was implemented on an AMD Alveo U250 Data Center Accelerator Card, and was evaluated against the B+ tree search algorithm from the TLX library running on an AMD EPYC 7542 processor (2.9 GHz). With a batch size of 1000 search keys, a B+ tree containing one million entries, and a tree order of 16, we measured a 4.9x speedup for the single-kernel FPGA design compared to a single-threaded CPU implementation. Running four kernel instances in parallel on the FPGA resulted in a 2.1$\times$ performance improvement over a CPU implementation using 16 threads.

翻译：本文提出一种基于B+树索引结构的搜索算法，该算法针对现场可编程门阵列（FPGA）执行进行了专门优化。我们的实现通过逐层处理一批搜索键，高效遍历并重用树节点。该方法减少了代价高昂的全局内存访问，提升了已加载B+树节点的重用率，并实现了在FPGA上直接对搜索键进行并行比较。采用高层次综合（HLS）方法，我们开发了一个高度灵活且可配置的搜索内核设计，支持可变批量大小、可定制的节点大小及任意树深度。最终设计在AMD Alveo U250数据中心加速卡上实现，并与TLX库中运行于AMD EPYC 7542处理器（2.9 GHz）上的B+树搜索算法进行了对比评估。在批量大小为1000个搜索键、B+树包含一百万条记录、树阶为16的条件下，单内核FPGA设计相比单线程CPU实现实现了4.9倍的加速。在FPGA上并行运行四个内核实例时，相比使用16线程的CPU实现性能提升了2.1$\times$。