Spike timing offers a combinatorial address space, suggesting that timing-based spiking inference can be executed as lookup and routing rather than as dense multiply--accumulate. Yet most neuromorphic and photonic systems still digitize events into timestamps, bins, or rates and then perform selection in clocked logic. We introduce Polychronous Wave Computing (PWC), a timing-native address-selection primitive that maps relative spike latencies directly to a discrete output route in the wave domain. Spike times are phase-encoded in a rotating frame and processed by a programmable multiport interferometer that evaluates K template correlations in parallel; a driven--dissipative winner-take-all stage then performs a physical argmax, emitting a one-hot output port. We derive the operating envelope imposed by phase wrapping and mutual coherence, and collapse timing jitter, static phase mismatch, and dephasing into a single effective phase-noise budget whose induced winner--runner-up margin predicts boundary-first failures and provides an intensity-only calibration target. Simulations show that nonlinear competition improves routing fidelity compared with noisy linear intensity readout, and that hardware-in-the-loop phase tuning rescues a temporal-order gate from 55.9% to 97.2% accuracy under strong static mismatch. PWC provides a fast routing coprocessor for LUT-style spiking networks and sparse top-1 gates (e.g., mixture-of-experts routing) across polaritonic, photonic, and oscillator platforms.

翻译：脉冲时序提供了一个组合地址空间，表明基于时序的脉冲推理可以像查找和路由那样执行，而非密集的乘加运算。然而，大多数神经形态和光子系统仍将事件数字化为时间戳、时间仓或脉冲频率，然后在时钟逻辑中执行选择。本文介绍了多时波计算（PWC），这是一种时序原生的地址选择原语，它将相对脉冲延迟直接映射到波域中的离散输出路径。脉冲时间在旋转坐标系中进行相位编码，并由可编程多端口干涉仪处理，该干涉仪并行评估K个模板相关性；随后，一个驱动-耗散赢家通吃级执行物理argmax操作，发射出一个独热编码的输出端口。我们推导了由相位卷绕和相互相干性所施加的工作范围，并将时序抖动、静态相位失配和退相干合并为一个单一的有效相位噪声预算，其引发的赢家-亚军裕度可预测边界优先失效，并提供一个仅基于强度的校准目标。仿真表明，与噪声线性强度读出相比，非线性竞争提高了路由保真度；在强静态失配下，硬件在环相位调谐能将时序门电路的准确率从55.9%提升至97.2%。PWC为LUT式脉冲网络和稀疏Top-1门电路（例如专家混合路由）提供了一个快速路由协处理器，适用于极化激元、光子和振荡器平台。