Logic synthesis is the first and most vital step in chip design. This steps converts a chip specification written in a hardware description language (such as Verilog) into an optimized implementation using Boolean logic gates. State-of-the-art logic synthesis algorithms have a large number of logic minimization heuristics, typically applied sequentially based on human experience and intuition. The choice of the order greatly impacts the quality (e.g., area and delay) of the synthesized circuit. In this paper, we propose INVICTUS, a model-based offline reinforcement learning (RL) solution that automatically generates a sequence of logic minimization heuristics ("synthesis recipe") based on a training dataset of previously seen designs. A key challenge is that new designs can range from being very similar to past designs (e.g., adders and multipliers) to being completely novel (e.g., new processor instructions). %Compared to prior work, INVICTUS is the first solution that uses a mix of RL and search methods joint with an online out-of-distribution detector to generate synthesis recipes over a wide range of benchmarks. Our results demonstrate significant improvement in area-delay product (ADP) of synthesized circuits with up to 30\% improvement over state-of-the-art techniques. Moreover, INVICTUS achieves up to $6.3\times$ runtime reduction (iso-ADP) compared to the state-of-the-art.

翻译：逻辑综合是芯片设计中首要且最关键的一步。该步骤将用硬件描述语言（如Verilog）编写的芯片规范，转化为使用布尔逻辑门的优化实现。最先进的逻辑综合算法包含大量逻辑最小化启发式方法，通常基于人类经验和直觉按顺序应用。这些方法的顺序选择会显著影响综合电路的质量（如面积和延迟）。本文提出INVICTUS，一种基于模型的离线强化学习（RL）解决方案，能够基于先前设计的数据集自动生成逻辑最小化启发式方法的序列（"综合配方"）。主要挑战在于新设计可能既包括与过去高度相似的设计（如加法器和乘法器），也包含完全新颖的设计（如新处理器指令）。与先前研究相比，INVICTUS是首个结合强化学习与搜索方法，并联合在线分布外检测器，能在广泛基准测试中生成综合配方的解决方案。实验结果表明，综合电路的面积-延迟积（ADP）获得显著提升，较最先进技术最高改善达30%。此外，与现有技术相比，INVICTUS在等面积-延迟积条件下实现了最高6.3倍的运行时间缩减。