Benefiting from performance advantages under short code lengths, polar codes are well-suited for certain scenarios, such as the future Internet of Things (IoT) applications that require high reliability and low power. Existing list flip decoders can efficiently further enhance the error-correction performance of polar codes with finite code lengths, particularly the dynamic successive cancellation list flip (D-SCLF) decoder with flexible high-order error-correction capability (FHECC). However, to the best of our knowledge, current list flip decoders cannot effectively balance complexity and error-correction efficiency. To address this, we propose a parity-check-aided D-SCLF (PC-DSCLF) decoder. This decoder, based on FHECC and the characteristics of the list flip decoding process, introduces a simplified flip metric and a hybrid check scheme, along with a decoding method that supports the check scheme, enabling it to retain FHECC while achieving low complexity. Simulation results show that the proposed PC-DSCLF decoder achieves up to a 51.1\% average complexity reduction compared to the D-SCLF algorithm with distributed CRC for $PC(512, 256+24)$

翻译：得益于短码长下的性能优势，极化码特别适用于某些场景，例如未来需要高可靠性和低功耗的物联网（IoT）应用。现有的列表翻转译码器能够有效进一步提升有限码长极化码的纠错性能，尤其是具有灵活高阶纠错能力（FHECC）的动态连续消除列表翻转（D-SCLF）译码器。然而，据我们所知，当前的列表翻转译码器无法有效平衡复杂度与纠错效率。为解决这一问题，我们提出了一种奇偶校验辅助的D-SCLF（PC-DSCLF）译码器。该译码器基于FHECC及列表翻转译码过程的特性，引入了简化的翻转度量和混合校验方案，以及一种支持该校验方案的译码方法，使其在保持FHECC的同时实现低复杂度。仿真结果表明，对于$PC(512, 256+24)$，所提出的PC-DSCLF译码器相较于采用分布式CRC的D-SCLF算法，平均复杂度最高可降低51.1\%。