High load latency that results from deep cache hierarchies and relatively slow main memory is an important limiter of single-thread performance. Data prefetch helps reduce this latency by fetching data up the hierarchy before it is requested by load instructions. However, data prefetching has shown to be imperfect in many situations. We propose cache-level prediction to complement prefetchers. Our method predicts which memory hierarchy level a load will access allowing the memory loads to start earlier, and thereby saves many cycles. The predictor provides high prediction accuracy at the cost of just one cycle added latency to L1 misses. Experimental results show speedup of 7.8\% on generic, graph, and HPC applications over a baseline with aggressive prefetchers.

翻译：由深缓存等级和相对缓慢的主内存产生的高负载延缓度是单线性能的重要限制。 数据预扩展有助于通过在按负载指示提出要求之前将数据从层次上获取, 从而降低这一延缓度。 然而, 数据预扩展显示在许多情形中是不完善的。 我们提出缓存级预测以补充预发货。 我们的方法预测了哪个内存级能让内存负量提前开始, 从而保存了许多周期。 预测器提供了高预测准确性, 仅以一次周期为代价为 L1 的误差添加延缓度。 实验结果显示, 在通用、 图形和 HPC 应用上, 加速了7. 8 ⁇, 以具有攻击性的预发货器的基线 。