In this paper we have addressed the implementation of the accumulation and projection of high-resolution event data stream (HD -1280 x 720 pixels) onto the image plane in FPGA devices. The results confirm the feasibility of this approach, but there are a number of challenges, limitations and trade-offs to be considered. The required hardware resources of selected data representations, such as binary frame, event frame, exponentially decaying time surface and event frequency, were compared with those available on several popular platforms from AMD Xilinx. The resulting event frames can be used for typical vision algorithms, such as object classification and detection, using both classical and deep neural network methods.

翻译：本文研究了在FPGA设备上将高分辨率事件数据流（HD-1280×720像素）累积并投影到图像平面上的实现方法。结果证实了该方法的可行性，但仍需考虑若干挑战、限制及权衡。本文比较了所选数据表示（如二值帧、事件帧、指数衰减时间表面及事件频率）所需的硬件资源与AMD Xilinx多款主流平台可用的硬件资源。生成的事件帧可用于典型的视觉算法（如目标分类与检测），兼容传统方法与深度神经网络方法。