Co-optimizing placement with congestion is integral to achieving high-quality designs. This paper presents GOALPlace, a new learning-based general approach to improving placement congestion by controlling cell density. Our method efficiently learns from an EDA tool's post-route optimized results and uses an empirical Bayes technique to adapt this goal/target to a specific placer's solutions, effectively beginning with the end in mind. It enhances correlation with the long-running heuristics of the tool's router and timing-opt engine -- while solving placement globally without expensive incremental congestion estimation and mitigation methods. A statistical analysis with a new hierarchical netlist clustering establishes the importance of density and the potential for an adequate cell density target across placements. Our experiments show that our method, integrated as a demonstration inside an academic GPU-accelerated global placer, consistently produces macro and standard cell placements of superior or comparable quality to commercial tools. Our empirical Bayes methodology also allows a substantial quality improvement over state-of-the-art academic mixed-size placers, achieving up to 10x fewer design rule check (DRC) violations, a 5% decrease in wirelength, and a 30% and 60% reduction in worst and total negative slack (WNS/TNS).

翻译：协同优化布局与拥塞是实现高质量设计的关键环节。本文提出GOALPlace——一种基于学习的通用新方法，通过控制单元密度来改善布局拥塞。该方法能有效从电子设计自动化工具的后布线优化结果中学习，并采用经验贝叶斯技术将该目标适配至特定布局器的解决方案，真正实现"以终为始"的优化理念。在避免使用昂贵的增量式拥塞估计与缓解方法的前提下，本方法通过全局布局求解，显著增强了与工具内部布线器和时序优化引擎长期启发性策略的关联性。基于新型层次化网表聚类技术的统计分析，证实了密度因素的重要性以及跨布局场景中设定适当单元密度目标的潜力。实验表明，本方法在学术级GPU加速全局布局器中集成演示时，持续生成优于或媲美商业工具的宏单元与标准单元布局方案。经验贝叶斯方法相较最先进的学术混合尺寸布局器实现了显著质量提升：设计规则检查违规减少高达10倍，线长降低5%，最差负时序裕量与总负时序裕量分别减少30%和60%。