Many modern workloads such as neural network inference and graph processing are fundamentally memory-bound. For such workloads, data movement between memory and CPU cores imposes a significant overhead in terms of both latency and energy. A major reason is that this communication happens through a narrow bus with high latency and limited bandwidth, and the low data reuse in memory-bound workloads is insufficient to amortize the cost of memory access. Fundamentally addressing this data movement bottleneck requires a paradigm where the memory system assumes an active role in computing by integrating processing capabilities. This paradigm is known as processing-in-memory (PIM). Recent research explores different forms of PIM architectures, motivated by the emergence of new technologies that integrate memory with a logic layer, where processing elements can be easily placed. Past works evaluate these architectures in simulation or, at best, with simplified hardware prototypes. In contrast, the UPMEM company has designed and manufactured the first publicly-available real-world PIM architecture. The UPMEM PIM architecture combines traditional DRAM memory arrays with general-purpose in-order cores, called DRAM Processing Units (DPUs), integrated in the same chip. This paper presents key takeaways from the first comprehensive analysis of the first publicly-available real-world PIM architecture. We provide four key takeaways about the UPMEM PIM architecture, which stem from our study. More insights about suitability of different workloads to the PIM system, programming recommendations for software designers, and suggestions and hints for hardware and architecture designers of future PIM systems are available in arXiv:2105.03814

翻译：许多现代工作负载（如神经网络推理和图处理）本质上受到内存限制。对于此类工作负载，内存与CPU核心之间的数据传输在延迟和能耗方面都造成了显著开销。其主要原因在于这种通信是通过窄带宽、高延迟的总线进行的，而内存受限工作负载的低数据复用性不足以摊销内存访问成本。从根本上解决这一数据移动瓶颈，需要一种内存系统通过集成处理能力来承担主动计算角色的范式，即“处理-内存”（PIM）。近期研究探索了不同类型的PIM架构，其动机源于将内存与逻辑层集成（处理单元可轻松布局）的新技术的出现。以往工作在仿真或最多通过简化硬件原型评估这些架构。相比之下，UPMEM公司设计并制造了首个公开可用的真实世界PIM架构。该架构将传统DRAM存储阵列与通用按序处理核心（称为DRAM处理单元，DPUs）集成在同一芯片中。本文呈现了对首个公开可用真实世界PIM架构的首次全面分析的关键见解。我们基于研究得出了关于UPMEM PIM架构的四点关键发现。关于不同工作负载对PIM系统适用性的更多见解、面向软件开发者的编程建议，以及面向未来PIM系统硬件和架构设计者的建议与提示，详见arXiv:2105.03814。