The recently proposed recursive projection-aggregation (RPA) decoding algorithm for Reed-Muller codes has received significant attention as it provides near-ML decoding performance at reasonable complexity for short codes. However, its complicated structure makes it unsuitable for hardware implementation. Iterative projection-aggregation (IPA) decoding is a modified version of RPA decoding that simplifies the hardware implementation. In this work, we present a flexible hardware architecture for the IPA decoder that can be configured from fully-sequential to fully-parallel, thus making it suitable for a wide range of applications with different constraints and resource budgets. Our simulation and implementation results show that the IPA decoder has 41% lower area consumption, 44% lower latency, four times higher throughput, but currently seven times higher power consumption for a code with block length of 128 and information length of 29 compared to a state-of-the-art polar successive cancellation list (SCL) decoder with comparable decoding performance.

翻译：近期提出的Reed-Muller码递归投影聚合（RPA）译码算法因其在短码条件下以合理复杂度实现接近最大似然（ML）译码性能而备受关注。然而其复杂结构导致硬件实现困难。迭代投影聚合（IPA）译码作为RPA译码的改进版本，简化了硬件实现方案。本文提出一种灵活可配置的IPA译码器硬件架构，支持从全串行到全并行的配置模式，适用于具有不同约束条件和资源预算的多种应用场景。仿真与实现结果表明，对于码块长度128、信息长度29的码字，相较于具有相当译码性能的先进极化码连续消除列表（SCL）译码器，该IPA译码器面积消耗降低41%，延迟降低44%，吞吐量提升四倍，但当前功耗为七倍。