The irregular nature of memory accesses of graph workloads makes their performance poor on modern computing platforms. On manycore reconfigurable architectures (MRAs), in particular, even state-of-the-art graph prefetchers do not work well (only 3% speedup), since they are designed for traditional CPUs. This is because caches in MRAs are typically not large enough to host a large quantity of prefetched data, and many employs shared caches that such prefetchers simply do not support. This paper studies the design of a data prefetcher for an MRA called Transmuter. The prefetcher is built on top of Prodigy, the current best-performing data prefetcher for CPUs. The key design elements that adapt the prefetcher to the MRA include fused prefetcher status handling registers and a prefetch handshake protocol to support run-time reconfiguration, in addition, a redesign of the cache structure in Transmuter. An evaluation of popular graph workloads shows that synergistic integration of these architectures outperforms a baseline without prefetcher by 1.27x on average and by as much as 2.72x on some workloads.

翻译：图计算工作负载内存访问的不规则性导致其在现代计算平台上性能表现不佳。在多核可重构架构（MRA）上，即便是最先进的图预取器（仅能提升3%性能）也难以有效工作，因为这些预取器专为传统CPU设计。这主要源于多核可重构架构的缓存通常不足以容纳大量预取数据，且多数采用共享缓存架构，使得预取器无法正常运作。本文研究了面向称为Transmuter的多核可重构架构的数据预取器设计。该预取器基于当前性能最优的CPU数据预取器Prodigy构建。适应多核可重构架构的关键设计要素包括：融合预取器状态处理寄存器、支持运行时重配置的预取握手协议，以及对Transmuter缓存结构的重新设计。对常见图工作负载的评估表明，这些架构的协同集成相比无预取器的基线方案平均提升1.27倍性能，部分工作负载的加速效果可达2.72倍。