We present a design automation framework for analog circuit sizing that produces calibrated, topology-specific analytical equations from raw circuit netlists. A large language model (LLM) derives a complete Python sizing function in which each device dimension is traceable to a specific design rationale - a form of interpretable output absent from existing optimization-based and LLM-based sizing methods. A deterministic calibration loop extracts process-dependent parameters from a single DC operating point simulation, while a prediction-error feedback mechanism compensates for analytical inaccuracies. We validate the framework on circuits ranging from 8 to 30 transistors - spanning two-stage Miller-compensated, current-mirror, folded cascode, nested Miller-compensated, and complementary class-AB output topologies - across three process nodes (40 nm, 90 nm, 180 nm). On matched-specification benchmarks, including the class-AB opamp case, the framework converges in 2-7 simulations. Despite large initial prediction errors, convergence depends on the measurement-feedback architecture, not prediction accuracy. The one-shot calibration automatically captures process-dependent variations, enabling cross-node portability without modification, retraining, or per-process characterization.

翻译：我们提出了一种用于模拟电路尺寸设计的自动化框架，该框架能从原始电路网表生成经校准的、与拓扑结构相关的解析方程。大型语言模型（LLM）推导出完整的Python尺寸函数，其中每个器件尺寸均可追溯至特定的设计原理——这是一种现有基于优化和基于LLM的尺寸方法所不具备的可解释输出形式。确定性校准环路通过单次直流工作点仿真提取工艺相关参数，同时预测误差反馈机制补偿解析模型的不准确性。我们在包含8至30个晶体管的电路上验证了该框架——涵盖两级米勒补偿、电流镜、折叠共源共栅、嵌套米勒补偿及互补AB类输出拓扑结构——并跨越三个工艺节点（40纳米、90纳米、180纳米）。在包含AB类运算放大器案例的匹配规格基准测试中，该框架在2-7次仿真内收敛。尽管初始预测误差较大，但收敛性取决于测量反馈架构而非预测精度。单次校准可自动捕获工艺相关变化，无需修改、重新训练或逐工艺表征即可实现跨节点可移植性。