Security is a growing problem that needs hardware support. Memristors provide an alternative technology for hardware-supported security implementation. This paper presents a specific technique that utilizes the benefits of hybrid CMOS-memristors technology demonstrated with SHA3 over implementations that use only memristor technology. In the proposed technique, SHA3 is implemented in a set of perpendicular crossbar arrays structured to facilitate logic implementation and circular bit rotation (Rho operation), which is perhaps the most complex operation in SHA3 when carried out in memristor arrays. The Rho operation itself is implemented with CMOS multiplexers (MUXs). The proposed accelerator is standby power-free and circumvents the memory access bottleneck in conventional computers. In addition, our design obscures the intermediate values from the I/O interface and outperforms the state-of-the-art memristor-based designs in terms of size and energy. Demonstrating the memristor implementation of SHA3 provides an impetus for utilizing memristors in information security applications.

翻译：安全是一个日益严峻的问题，需要硬件支持。忆阻器为硬件支撑的安全实现提供了一种替代技术。本文提出一种特定技术，利用混合CMOS-忆阻器技术的优势，通过SHA3算法在纯忆阻器技术实现方案中的对比进行验证。在所提出的技术中，SHA3实现于一组垂直交叉阵列结构中，该结构旨在促进逻辑实现与循环比特移位操作（Rho运算）——这可能是忆阻器阵列中执行SHA3时最复杂的操作。Rho运算本身采用CMOS多路复用器实现。所提出的加速器无需备用电源，并规避了传统计算机中的内存访问瓶颈。此外，我们的设计对I/O接口隐藏了中间值，且在尺寸和能耗方面优于现有最先进的忆阻器设计。对SHA3忆阻器实现的验证，为忆阻器在信息安全领域的应用提供了推动力。