Quantum computers have the potential to solve certain complex problems in a much more efficient way than classical computers. Nevertheless, current quantum computer implementations are limited by high physical error rates. This issue is addressed by Quantum Error Correction (QEC) codes, which use multiple physical qubits to form a logical qubit to achieve a lower logical error rate, with the surface code being one of the most commonly used. The most time-critical step in this process is interpreting the measurements of the physical qubits to determine which errors have most likely occurred - a task called decoding. Consequently, the main challenge for QEC is to achieve error correction with high accuracy within the tight $1μs$ decoding time budget imposed by superconducting qubits. State-of-the-art QEC approaches trade accuracy for latency. In this work, we propose an FPGA accelerator for a Neural Network based decoder as a way to achieve a lower logical error rate than current methods within the tight time constraint, for code distance up to d=7. We achieved this goal by applying different hardware-aware optimizations to a high-accuracy GNN-based decoder. In addition, we propose several accelerator optimizations leading to the FPGA-based decoder achieving a latency smaller than $1μs$, with a lower error rate compared to the state-of-the-art.

翻译：量子计算机有潜力以比经典计算机高效得多的方式解决某些复杂问题。然而，当前量子计算机实现受限于高物理错误率。量子纠错（QEC）码通过使用多个物理量子比特构成一个逻辑量子比特以实现更低的逻辑错误率来解决此问题，其中表面码是最常用的方案之一。此过程中最耗时的关键步骤是解读物理量子比特的测量结果，以确定最可能发生的错误类型——这一任务被称为解码。因此，QEC的主要挑战是在超导量子比特所施加的严格$1μs$解码时间预算内，实现高精度的纠错。最先进的QEC方法牺牲精度以换取延迟。在本工作中，我们提出一种基于神经网络解码器的FPGA加速器，旨在在严格时间约束下，针对码距d≤7的情况，实现低于当前方法的逻辑错误率。我们通过对一个高精度基于GNN的解码器应用不同的硬件感知优化实现了这一目标。此外，我们提出了多项加速器优化，使得基于FPGA的解码器延迟小于$1μs$，且错误率比现有最先进方法更低。