Quantum error correction (QEC) is essential for realizing large-scale, fault-tolerant quantum computation, yet its practical implementation remains a major engineering challenge. In particular, QEC demands precise real-time control of a large number of qubits and low-latency, high-throughput and accurate decoding of error syndromes. While most prior work has focused primarily on decoder design, the overall performance of any QEC system depends critically on all its subsystems including control, communication, and decoding, as well as their integration. To address this challenge, we present an open-source, fully integrated QEC system built on RISC-Q, a generator for RISC-V-based quantum control architectures. Implemented on RFSoC FPGAs, our system prototype integrates real-time qubit control, a scalable distributed multi-board architecture, and the state-of-the-art hardware QEC decoder within a low-latency, high-throughput decoding pipeline, forming a complete hardware platform ready for deployment with superconducting qubits. Experimental evaluation on a three-board prototype based on AMD ZCU216 RFSoCs demonstrates an end-to-end QEC decoding-feedback latency of 446 ns for a distance-3 surface code, including syndrome aggregation, network communication, syndrome decoding, and error distribution. Extrapolating from measured subsystem performance and state-of-the-art decoder benchmarks, the architecture can achieve sub-microsecond decoding-feedback latency up to a distance-21 surface code ($\sim$881 physical qubits) when scaled to larger hardware configurations.

翻译：量子纠错（QEC）是实现大规模容错量子计算的关键，但其实际实施仍面临重大工程挑战。具体而言，QEC需要对大量量子比特进行精确的实时控制，并对错误症候进行低延迟、高吞吐量且精确的解码。尽管先前研究主要聚焦于解码器设计，但任何QEC系统的整体性能关键取决于其所有子系统（包括控制、通信与解码）及其集成方式。为应对这一挑战，我们提出一种基于RISC-Q（基于RISC-V的量子控制架构生成器）构建的开源全集成QEC系统。该系统原型在RFSoC FPGA上实现，集成了实时量子比特控制、可扩展分布式多板卡架构，以及最先进的硬件QEC解码器，形成具备低延迟高吞吐量解码流水线的完整硬件平台，可直接部署于超导量子比特体系。基于AMD ZCU216 RFSoC的三板卡原型实验评估表明：针对距离为3的表面码，其端到端QEC解码反馈延迟（包括症候聚合、网络通信、症候解码与错误分发）仅为446纳秒。根据实测子系统性能与最先进解码器基准数据推断，该架构在扩展至更大硬件配置时，可对距离达21的表面码（约881个物理量子比特）实现亚微秒级解码反馈延迟。