Large-scale quantum computers promise transformative speedups, but their viability hinges on fast and reliable quantum error correction (QEC). At the center of QEC are decoders-classical algorithms running on hardware such as FPGAs, GPUs, or CPUs that process error syndromes to detect errors every microsecond to preserve fault-tolerance. Quantum processors, therefore, operate not in isolation, but as accelerators tightly coupled with powerful classical digital hardware. A key challenge is that decoder demand fluctuates unpredictably: bursts of activity can require orders of magnitude more decodes than idle periods. Provisioning hardware for the worst case wastes resources, while provisioning for the average case risks catastrophic slowdowns. We show that this mismatch is a systems problem of capacity planning and scheduling, and propose a two-level framework that treats decoders as shared accelerators managed by the quantum operating system. Our approach reduces decoder requirements by 10-40% across fault-tolerant benchmarks, demonstrating that efficient decoder scheduling is essential to making FTQC practical.

翻译：大规模量子计算机有望带来变革性的加速，但其可行性依赖于快速可靠的量子纠错。QEC的核心是解码器——运行在FPGA、GPU或CPU等硬件上的经典算法，这些算法每微秒处理错误症状以检测错误，从而维持容错能力。因此，量子处理器并非独立运行，而是作为与强大经典数字硬件紧密耦合的加速器。一个关键挑战在于解码器需求存在不可预测的波动：突发活动可能比空闲时段需要多出数个数量级的解码操作。为最坏情况配置硬件会浪费资源，而为平均情况配置则可能引发灾难性减速。我们证明这种不匹配是容量规划与调度的系统问题，并提出一个将解码器视为由量子操作系统管理的共享加速器的双层框架。我们的方法在容错基准测试中将解码器需求降低了10-40%，证明高效解码器调度是实现实用化容错量子计算的关键。