The automation of analog integrated circuit (IC) design remains a longstanding challenge, primarily due to the intricate interdependencies among physical layout, parasitic effects, and circuit-level performance. These interactions impose complex constraints that are difficult to accurately capture and optimize using conventional design methodologies. Although recent advances in machine learning (ML) have shown promise in automating specific stages of the analog design flow, the development of holistic, end-to-end frameworks that integrate these stages and iteratively refine layouts using post-layout, parasitic-aware performance feedback is still in its early stages. Furthermore, progress in this direction is hindered by the limited availability of open, high-quality datasets tailored to the analog domain, restricting both the benchmarking and the generalizability of ML-based techniques. To address these limitations, we present OSIRIS, a scalable dataset generation pipeline for analog IC design. OSIRIS systematically explores the design space of analog circuits while producing comprehensive performance metrics and metadata, thereby enabling ML-driven research in electronic design automation (EDA). In addition, we release a dataset consisting of 87,100 circuit variations generated with OSIRIS, accompanied by a reinforcement learning (RL)-based baseline method that exploits OSIRIS for analog design optimization.

翻译：模拟集成电路（IC）设计的自动化仍然是一个长期存在的挑战，这主要源于物理版图、寄生效应与电路级性能之间复杂的相互依赖关系。这些相互作用施加了难以通过传统设计方法准确捕获和优化的复杂约束。尽管机器学习（ML）的最新进展在自动化模拟设计流程的特定阶段显示出潜力，但能够整合这些阶段并利用后版图、考虑寄生效应的性能反馈迭代优化版图的整体端到端框架仍处于早期发展阶段。此外，该方向的进展受到为模拟领域定制的开放、高质量数据集可用性有限的阻碍，这制约了基于ML技术的基准测试和泛化能力。为应对这些局限，我们提出了OSIRIS，一个用于模拟IC设计的可扩展数据集生成流程。OSIRIS系统地探索模拟电路的设计空间，同时生成全面的性能指标和元数据，从而赋能电子设计自动化（EDA）领域的ML驱动研究。此外，我们发布了一个包含87,100个由OSIRIS生成的电路变体的数据集，并附带一种基于强化学习（RL）的基线方法，该方法利用OSIRIS进行模拟设计优化。