CXL has been the emerging technology for expanding memory for both the host CPU and device accelerators with load/store interface. Extending memory coherency to the PCIe root complex makes the codesign more flexible in that you can access the memory with coherency using your near-device computability. Since the capacity demand with tolerable latency and bandwidth is growing, we need to come up with a new hardware-software codesign way to offload the synthesized memory operations to the CXL endpoint, CXL switch or near CXL root complex cores like Intel DSA to fetch data; the CPU or accelerators can calculate other stuff in the backend. On CXL done loading, the data will be put into L1 if capacity fits, and the in-core ROB will be notified by mailbox and resume the calculation on the previous hardware context. Since the distance(timing window) of the load instruction sequence is unknown, a profiling-guided way of codegening and adaptively updating offloaded code will be required for a long-running job. We propose to evaluate CXLMemUring the modified BOOMv3 with added in-core-logic and CXL endpoint access simulation using CHI, and we will add a weaker RISCV Core near endpoint for code offloading, and the codegening will be based on program analysis with traditional profiling guided way.

翻译：CXL已成为通过加载/存储接口为主机CPU与设备加速器扩展内存的新兴技术。将内存一致性扩展至PCIe根复合体使得协同设计更具灵活性——利用近设备计算能力即可实现带一致性的内存访问。随着对可容忍延迟与带宽下的容量需求持续增长，亟需设计新型软硬件协同方式，将合成内存操作卸载至CXL端点、CXL交换机或如Intel DSA等靠近CXL根复合体的核心进行数据预取；而CPU或加速器可在后端并行执行其他计算任务。当CXL加载完成后，若L1缓存容量允许，数据将被存入其中；同时通过邮箱机制通知核内重排序缓冲器（ROB），使其恢复基于之前硬件上下文的计算。由于加载指令序列的时序窗口存在不确定性，对于长时运行任务，需采用基于性能剖析引导的代码生成与自适应更新卸载代码方法。我们提出评估CXLMemUring——基于CHI协议实现扩展核内逻辑与CXL端点访问模拟的改进型BOOMv3架构，并将在端点附近增设弱化RISC-V核心用于代码卸载；代码生成将基于传统性能剖析引导的程序分析策略。