Research into the development of special-purpose computing architectures designed to solve quadratic unconstrained binary optimization (QUBO) problems has flourished in recent years. It has been demonstrated in the literature that such special-purpose solvers can outperform traditional complementary metal--oxide--semiconductor architectures by orders of magnitude with respect to timing metrics on synthetic problems. However, they face challenges with constrained problems such as the quadratic assignment problem (QAP), where mapping to binary formulations such as QUBO introduces overhead and limits parallelism. In-memory computing (IMC) devices, such as memristor-based analog Ising machines, offer significant speed-ups and efficiency gains over traditional CPU-based solvers, particularly for solving combinatorial optimization problems. In this work, we present a novel hardware-aware QAP optimization framework designed for IMC hardware. By co-designing the local search heuristic with the underlying hardware, we exploit the intrinsic massive parallelism that allows for computing of full neighbourhoods simultaneously to make update decisions. We ensure binary solutions remain feasible by selecting local moves that lead to neighbouring feasible solutions, leveraging feasible-space search heuristics and the underlying structure of a given problem. Our approach is compatible with both digital computers and analog hardware. We demonstrate its effectiveness in CPU implementations by comparing it with state-of-the-art heuristics for solving the QAP.

翻译：近年来，针对求解无约束二元二次优化问题的专用计算架构研究蓬勃发展。文献研究表明，这类专用求解器在合成问题上相比传统互补金属氧化物半导体架构，在时序指标上可实现数个数量级的性能提升。然而，当面对二次分配问题这类带约束优化问题时，将其映射为QUBO等二元形式会带来额外开销并限制并行性。基于忆阻器的模拟伊辛机等内存计算设备，相较于传统CPU求解器，在求解组合优化问题方面展现出显著的加速效果与能效优势。本文提出一种面向IMC硬件的新型硬件感知QAP优化框架。通过协同设计局部搜索启发式策略与底层硬件，我们利用其固有的海量并行性同时计算完整邻域以做出更新决策。通过选择能导向可行邻域解的局部移动策略，并借助可行域搜索启发式算法与给定问题的底层结构，确保二元解始终满足可行性约束。本方法兼具数字计算机与模拟硬件的兼容性。通过对比求解QAP的最优启发式算法，我们在CPU实现中验证了其有效性。