Binary multipliers have long been a staple component in digital circuitry, serving crucial roles in microprocessor design, digital signal processing units and many more applications. This work presents a unique design for a multiplier that utilizes a reformed-array-logic approach to compute the product of two unsigned binary numbers. We employed a multiplexer and a barrel shifter to multiply partial products in a single clock cycle to speed up the traditional array logic. In addition, we have employed a combination of Carry Save Adders (CSA) and Ripple Carry Adders (RCA) to accumulate the partial products instead of using standalone RCAs to speed up the multiplication process further. Finally, we have demonstrated our design to perform multiplication of two 16-bit unsigned binary numbers on Cadence Virtuoso. Our design is modular and can be scaled up or down to accommodate the multiplication of any n-bit unsigned numbers.

翻译：二进制乘法器长期以来一直是数字电路中的核心组件，在微处理器设计、数字信号处理单元等诸多应用中发挥着关键作用。本研究提出了一种独特的乘法器设计，采用改进的阵列逻辑方法计算两个无符号二进制数的乘积。我们通过复用器和桶形移位器在单时钟周期内计算部分积，从而加速传统阵列逻辑的运算过程。此外，我们采用进位保留加法器（CSA）与行波进位加法器（RCA）的组合来累加部分积，而非单独使用RCA，从而进一步加速乘法运算。最后，我们在Cadence Virtuoso平台上验证了该设计对两个16位无符号二进制数的乘法运算性能。该设计采用模块化架构，可通过扩展或缩减适配任意n位无符号数的乘法运算需求。