This work introduces and characterizes quantum sequential circuits (QSCs) as a hardware-oriented paradigm for quantum computing, built upon a novel foundational element termed the quantum transistor. Unlike conventional qubit-based architectures, QSCs employ symmetry-protected topological junctions where quantum gates are encoded as Choi states via channel-state duality and activated through bulk measurements, utilizing ebits to realize the functional analog of feedback loops in classical sequential circuits. This framework establishes a universal model for quantum computation that inherently incorporates memory and temporal sequencing, complementing existing combinational quantum circuit model. Our work advances the conceptual bridge towards a quantum von Neumann architecture, underscoring the potential of hybrid and modular design principles for the development of large-scale, integrated quantum information processors.

翻译：本研究提出并刻画了量子时序电路（QSCs）作为一种面向硬件的量子计算范式，其构建于一种称为量子晶体管的新型基础元件之上。与传统的基于量子比特的架构不同，QSCs采用对称性保护的拓扑结，其中量子门通过信道-态对偶性编码为Choi态，并通过体测量激活，利用纠缠比特来实现经典时序电路中反馈环的功能模拟。该框架建立了一个普遍适用的量子计算模型，其内在地包含了存储和时序序列，从而对现有的组合量子电路模型形成了补充。我们的工作推进了通往量子冯·诺依曼架构的概念桥梁，强调了混合与模块化设计原则对于开发大规模集成量子信息处理器的潜力。