As the modern CPU, GPU, and NPU chip design complexity and transistor counts keep increasing, and with the relentless shrinking of semiconductor technology nodes to nearly 1 nanometer, the placement and routing have gradually become the two most pivotal processes in modern very-large-scale-integrated (VLSI) circuit back-end design. How to evaluate routability efficiently and accurately in advance (at the placement and global routing stages) has grown into a crucial research area in the field of artificial intelligence (AI) assisted electronic design automation (EDA). In this paper, we propose a novel U-Net variant model boosted by an Inception embedded module to predict Routing Congestion (RC) and Design Rule Checking (DRC) hotspots. Experimental results on the recently published CircuitNet dataset benchmark show that our proposed method achieves up to 5% (RC) and 20% (DRC) rate reduction in terms of Avg-NRMSE (Average Normalized Root Mean Square Error) compared to the classic architecture. Furthermore, our approach consistently outperforms the prior model on the SSIM (Structural Similarity Index Measure) metric.

翻译：随着现代CPU、GPU及NPU芯片设计复杂度与晶体管数量持续攀升，加之半导体工艺节点不断逼近1纳米极限，布局与布线已逐渐成为超大规模集成电路后端设计中最关键的两个环节。如何在布局和全局布线阶段提前高效准确地评估可布线性，已成为人工智能辅助电子设计自动化领域的重要研究方向。本文提出了一种由Inception嵌入模块增强的新型U-Net变体模型，用于预测布线拥塞和设计规则检查热点。在最新发布的CircuitNet数据集基准上的实验结果表明，与经典架构相比，本文方法在平均归一化均方根误差指标上实现了最高5%（RC）和20%（DRC）的降幅。此外，所提方法在结构相似性度量指标上持续超越先前模型。