The increasing complexity of modern very-large-scale integration (VLSI) design highlights the significance of Electronic Design Automation (EDA) technologies. Chip placement is a critical step in the EDA workflow, which positions chip modules on the canvas with the goal of optimizing performance, power, and area (PPA) metrics of final chip designs. Recent advances have demonstrated the great potential of AI-based algorithms in enhancing chip placement. However, due to the lengthy workflow of chip design, the evaluations of these algorithms often focus on intermediate surrogate metrics, which are easy to compute but frequently reveal a substantial misalignment with the end-to-end performance (i.e., the final design PPA). To address this challenge, we introduce ChiPBench, which can effectively facilitate research in chip placement within the AI community. ChiPBench is a comprehensive benchmark specifically designed to evaluate the effectiveness of existing AI-based chip placement algorithms in improving final design PPA metrics. Specifically, we have gathered 20 circuits from various domains (e.g., CPU, GPU, and microcontrollers). These designs are compiled by executing the workflow from the verilog source code, which preserves necessary physical implementation kits, enabling evaluations for the placement algorithms on their impacts on the final design PPA. We executed six state-of-the-art AI-based chip placement algorithms on these designs and plugged the results of each single-point algorithm into the physical implementation workflow to obtain the final PPA results. Experimental results show that even if intermediate metric of a single-point algorithm is dominant, while the final PPA results are unsatisfactory. We believe that our benchmark will serve as an effective evaluation framework to bridge the gap between academia and industry.

翻译：现代超大规模集成电路（VLSI）设计日益增长的复杂性突显了电子设计自动化（EDA）技术的重要性。芯片布局是EDA工作流中的关键步骤，其目标是在画布上放置芯片模块，以优化最终芯片设计的性能、功耗和面积（PPA）指标。近期进展表明，基于人工智能的算法在增强芯片布局方面具有巨大潜力。然而，由于芯片设计工作流程漫长，对这些算法的评估通常侧重于易于计算但常与端到端性能（即最终设计PPA）存在显著偏差的中间代理指标。为应对这一挑战，我们提出了ChiPBench，它能有效促进人工智能领域内芯片布局相关的研究。ChiPBench是一个综合性基准测试套件，专门用于评估现有基于人工智能的芯片布局算法在改进最终设计PPA指标方面的有效性。具体而言，我们收集了来自不同领域（如CPU、GPU和微控制器）的20个电路设计。这些设计通过执行从Verilog源代码开始的工作流程进行编译，保留了必要的物理实现工具包，从而能够评估布局算法对最终设计PPA的影响。我们在这些设计上运行了六种最先进的基于人工智能的芯片布局算法，并将每个单点算法的结果接入物理实现工作流以获得最终的PPA结果。实验结果表明，即使某个单点算法的中间指标占优，其最终的PPA结果也可能不尽如人意。我们相信，我们的基准测试将作为一个有效的评估框架，弥合学术界与工业界之间的鸿沟。