High-level synthesis (HLS) notably speeds up the hardware design process by avoiding RTL programming. However, the turnaround time of HLS increases significantly when post-route quality of results (QoR) are considered during optimization. To tackle this issue, we propose a hierarchical post-route QoR prediction approach for FPGA HLS, which features: (1) a modeling flow that directly estimates latency and post-route resource usage from C/C++ programs; (2) a graph construction method that effectively represents the control and data flow graph of source code and effects of HLS pragmas; and (3) a hierarchical GNN training and prediction method capable of capturing the impact of loop hierarchies. Experimental results show that our method presents a prediction error of less than 10% for different types of QoR metrics, which gains tremendous improvement compared with the state-of-the-art GNN methods. By adopting our proposed methodology, the runtime for design space exploration in HLS is shortened to tens of minutes and the achieved ADRS is reduced to 6.91% on average.

翻译：高层次综合（HLS）通过避免RTL编程显著加速了硬件设计流程。然而，当在优化过程中考虑布线后质量结果（QoR）时，HLS的迭代周期会显著增加。为应对这一问题，我们提出了一种面向FPGA HLS的分层布线后QoR预测方法，其特点包括：（1）一种直接从C/C++程序估计延迟和布线后资源使用的建模流程；（2）一种有效表示源代码控制与数据流图及HLS编译指示效果的图构建方法；（3）一种能够捕捉循环层次影响的分层GNN训练与预测方法。实验结果表明，针对不同类型的QoR指标，本方法的预测误差均低于10%，相较于现有最先进的GNN方法取得了显著提升。采用本方法后，HLS设计空间探索的运行时间缩短至数十分钟，且平均ADRS降低至6.91%。