In many applications, the ability of current references to cope with process, voltage, and temperature (PVT) variations is critical to maintaining system-level performance. However, temperature-independent current references operating in the nA range are rarely area-efficient due to the use of large resistors which occupy a significant silicon area at this current level. In this article, we introduce a nA-range constant-with-temperature (CWT) current reference relying on a self-cascode MOSFET (SCM), biased by a proportional-to-absolute-temperature (PTAT) voltage with a CWT offset. On the one hand, the proposed reference has been simulated post-layout in 65-nm bulk. This design consumes 5.4 nW at 0.7 V and achieves a 1.1-nA current with a line sensitivity (LS) of 0.69 %/V and a temperature coefficient (TC) of 213 ppm/$^\circ$C. On the other hand, the proposed reference has been simulated and fabricated in 22-nm fully depleted silicon-on-insulator (FDSOI). This second design requires additional features to mitigate the impact of parasitic diode leakage at high temperature. In measurement, it consumes 5.8 nW at 0.9 V and achieves a 0.9-nA current with a 0.39-%/V LS and a 565-ppm/$^\circ$C TC. As a result of using an SCM, the proposed references occupy a silicon area of 0.0021 mm$^2$ in 65 nm (respectively, 0.0132 mm$^2$ in 22 nm) at least 25$\times$ (respectively, 4$\times$) smaller than state-of-the-art CWT references operating in the same current range.

翻译：在许多应用中，电流基准应对工艺、电压和温度变化的稳定性对维持系统级性能至关重要。然而，工作在纳安量级的温度无关电流基准由于需要大电阻（在该电流水平下占据显著硅面积）而难以实现面积高效。本文提出一种基于自级联MOSFET的纳安级恒温电流基准，其由带恒温偏移的PTAT电压偏置。一方面，所提基准在65nm体硅工艺中进行后布局仿真。该设计在0.7V电源电压下功耗为5.4nW，输出1.1nA电流，线性灵敏度为0.69%/V，温度系数为213ppm/°C。另一方面，所提基准在22nm全耗尽绝缘体上硅工艺中完成仿真与流片。第二版设计需额外引入特性以抑制高温下寄生二极管漏电流的影响。实测结果显示，该设计在0.9V电源电压下功耗为5.8nW，输出0.9nA电流，线性灵敏度为0.39%/V，温度系数为565ppm/°C。得益于SCM结构，所提基准在65nm工艺中占据0.0021mm²硅面积（22nm工艺中对应0.0132mm²），相比同电流范围工作的最先进CWT基准，面积缩小至少25倍（对应4倍）。