While leveraging LLMs to automatically generate SystemVerilog assertions (SVAs) from natural language specifications holds great potential, existing techniques face a key challenge: LLMs often lack sufficient understanding of IC design, leading to poor assertion quality in a single pass. Therefore, verifying whether the generated assertions effectively cover the functional specifications and designing feedback mechanisms based on this coverage remain significant hurdles. To address these limitations, this paper introduces CoverAssert, a novel iterative framework for optimizing SVA generation with LLMs. The core contribution is a lightweight mechanism for matching generated assertions with specific functional descriptions in the specifications. CoverAssert achieves this by clustering the joint representations of semantic features of LLM-generated assertions and structural features extracted from abstract syntax trees (ASTs) about signals related to assertions, and then mapping them back to the specifications to analyze functional coverage quality. Leveraging this capability, CoverAssert constructs a feedback loop based on functional coverage to guide LLMs in prioritizing uncovered functional points, thereby iteratively improving assertion quality. Experimental evaluations on four open-source designs demonstrate that integrating CoverAssert with state-of-the-art generators, AssertLLM and Spec2Assertion, achieves average improvements of 9.57 % in branch coverage, 9.64 % in statement coverage, and 15.69 % in toggle coverage.

翻译：尽管利用大型语言模型（LLM）从自然语言规约自动生成SystemVerilog断言（SVA）具有巨大潜力，但现有技术面临一个关键挑战：LLM通常对集成电路设计理解不足，导致单次生成的断言质量较差。因此，验证生成的断言是否能有效覆盖功能规约，并基于此覆盖率设计反馈机制，仍是亟待解决的重要难题。为应对这些局限，本文提出CoverAssert——一种基于LLM的迭代式SVA生成优化框架。其核心贡献在于一种轻量级机制，用于将生成的断言与规约中特定功能描述进行匹配。CoverAssert通过聚类LLM生成断言的语义特征与从抽象语法树（AST）中提取的断言相关信号结构特征的联合表示，并将其映射回规约以分析功能覆盖率质量，从而实现这一目标。依托此能力，CoverAssert构建了基于功能覆盖率的反馈循环，引导LLM优先处理未覆盖的功能点，从而迭代提升断言质量。在四个开源设计上的实验评估表明，将CoverAssert与前沿生成器AssertLLM和Spec2Assertion结合后，在分支覆盖率、语句覆盖率和翻转覆盖率上分别平均提升了9.57%、9.64%和15.69%。