Driven by a need for ever increasing chip performance and inclusion of innovative features, a growing number of semiconductor companies are opting for all-inclusive System-on-Chip (SoC) architectures. Although Moore's Law has been able to keep up with the demand for more complex logic, manufacturing large dies still poses a challenge. Increasingly the solution adopted to minimize the impact of silicon defects on manufacturing yield has been to split a design into multiple smaller dies called chiplets which are then brought together on a silicon interposer. Advanced 2.5D and 3D packaging techniques that enable this kind of integration also promise increased power efficiency and opportunities for heterogeneous integration. However, despite their advantages, chiplets are not without issues. Apart from manufacturing challenges that come with new packaging techniques, disaggregating a design into multiple logically and physically separate dies introduces new threats, including the possibility of tampering with and probing exposed data lines. In this paper we evaluate the exposure of chiplets to probing by applying laser contactless probing techniques to a chiplet-based AMD/Xilinx VU9P FPGA. First, we identify and map interposer wire drivers and show that probing them is easier compared to probing internal nodes. Lastly, we demonstrate that delay-based sensors, which can be used to protect against physical probes, are insufficient to protect against laser probing as the delay change due to laser probing is only 0.792ps even at 100\% laser power.

翻译：随着对芯片性能日益增长的需求以及对创新特性的追求，越来越多的半导体公司选择采用全集成系统级芯片（SoC）架构。尽管摩尔定律能够满足对更复杂逻辑的需求，但制造大尺寸晶圆仍然面临挑战。为减少硅缺陷对制造良率的影响，业界越来越多地采用将设计拆分为多个称为芯粒（chiplet）的小型晶圆，并通过硅中介层将其集成的解决方案。实现此类集成的先进2.5D和3D封装技术不仅有望提高能效，还为异构集成提供了可能。然而，尽管具有优势，芯粒技术并非没有缺陷。除了新封装技术带来的制造挑战外，将设计分解为多个逻辑和物理分离的晶圆会引入新的威胁，包括篡改和探测暴露数据线的可能性。本文通过将激光非接触式探测技术应用于基于芯粒的AMD/Xilinx VU9P FPGA，评估了芯粒面临的探测风险。首先，我们识别并映射了中介层导线驱动器，并证明相较于探测内部节点，探测这些驱动器更为容易。最后，我们论证了基于延迟的传感器（可用于防范物理探测）不足以防御激光探测，因为即使在100%激光功率下，激光探测引起的延迟变化仅为0.792ps。