The deployment of Large Language Models (LLMs) for real-time intelligence on edge devices is rapidly growing. However, conventional hardware architectures face a fundamental memory wall challenge, where limited on-device memory capacity and bandwidth severely constrain the size of deployable models and their inference speed, while also limiting on-device adaptation. To address this challenge, we propose TOM, a hybrid ROM-SRAM accelerator co-designed with ternary quantization, which balances extreme density with on-device tunability. TOM exploits the synergy between ternary quantization and ROM to achieve extreme memory density and bandwidth, while preserving flexibility through a hybrid ROM-SRAM architecture designed for QLoRA-based tunability. Specifically, we introduce: (1) a sparsity-aware ROM architecture that synthesizes ternary weights as standard-cell logic, eliminating area overhead from zero-valued bits; (2) a distributed processing architecture that co-locates high-density ROM banks with flexible SRAM-based QLoRA adapters and compute units; and (3) a workload-aware dynamic power gating scheme that exploits the logic-based nature of ROM to power down inactive banks, minimizing dynamic energy consumption. TOM achieves an inference throughput of 3,306 TPS using BitNet-2B model, demonstrating its effectiveness in delivering real-time, energy-efficient edge intelligence.

翻译：大型语言模型在边缘设备上实现实时智能的部署正在快速增长。然而，传统硬件架构面临根本性的内存墙挑战：有限的设备端内存容量和带宽严重制约了可部署模型的规模及其推理速度，同时也限制了设备端自适应能力。为应对这一挑战，我们提出TOM——一种与三态量化协同设计的混合ROM-SRAM加速器，在极致密度与设备端可调性之间取得平衡。TOM利用三态量化与ROM的协同效应，在实现极致内存密度和带宽的同时，通过专为基于QLoRA的可调性设计的混合ROM-SRAM架构保持灵活性。具体而言，我们提出：（1）稀疏感知ROM架构，将三态权重合成为标准单元逻辑，消除零值比特带来的面积开销；（2）分布式处理架构，将高密度ROM存储体与基于SRAM的灵活QLoRA适配器及计算单元就近部署；（3）工作负载感知的动态功耗门控方案，利用ROM基于逻辑的特性关闭非活跃存储体，最小化动态能耗。TOM使用BitNet-2B模型实现了3,306 TPS的推理吞吐量，证明了其在提供实时高效边缘智能方面的有效性。