The datacenter industry is converging on SmartNIC-based resource management. Wave (Humphries et al., ASPLOS '25) demonstrates the practical feasibility of offloading kernel thread scheduling, memory management, and RPC stacks to the ARM cores of Intel's Mount Evans Infrastructure Processing Unit (IPU). The engineering is careful and the results are honest: without Wave's PCIe latency mitigations, offloaded workloads degrade by 350%. We argue that this 350% degradation is not an engineering problem to be optimized away but a diagnostic symptom of a deeper architectural issue: Wave's communication model is Forward-In-Time-Only (FITO). Every interaction between host and SmartNIC is a unidirectional message -- event forward, decision back -- creating a temporal vulnerability window in which decisions can become stale before they are enforced. Wave's entire optimization stack (write-combining page table entries, prestaging, prefetching, atomic transaction abort) exists to hide or tolerate this window. We apply the FITO diagnostic to Wave's architecture systematically, identify the category mistake it inherits from Lamport's happened-before and Shannon's channel model, and show how Open Atomic Ethernet's bilateral swap primitive -- implemented on the same Intel IPU hardware -- dissolves the latency, atomicity, and timeout problems without engineering around them. The SmartNIC is the right location for resource management; what is missing is the right communication primitive at that location.

翻译：数据中心行业正趋向于采用基于智能网卡的资源管理方案。Wave（Humphries等人，ASPLOS '25）展示了将内核线程调度、内存管理和RPC栈卸载至英特尔Mount Evans基础设施处理单元ARM核心的实际可行性。其工程实现严谨且结果可靠：若无Wave的PCIe延迟缓解机制，卸载工作负载性能将下降350%。我们认为，这350%的性能下降并非可通过工程优化消除的技术问题，而是一个更深层架构缺陷的诊断性症状：Wave的通信模型采用仅前向时间模式。主机与智能网卡间的每次交互均为单向消息——事件前传、决策回传——这造成了决策在生效前即可能过时的时间脆弱窗口。Wave的整套优化机制（写合并页表项、预置处理、预取、原子事务中止）均旨在掩盖或容忍此窗口。我们系统性地将仅前向时间诊断框架应用于Wave架构，指出其承袭自Lamport"事前发生"关系与香农信道模型的范畴错误，并论证基于相同英特尔IPU硬件实现的开放原子以太网双向交换原语如何从根本上消解延迟、原子性与超时问题，而非通过工程手段规避。智能网卡确是资源管理的理想载体，当前缺失的正是该载体所需的正确通信原语。