The datacenter industry is converging on SmartNIC-based resource management. Wave (Humphries et al., ASPLOS '25) demonstrates the practical feasibility of offloading kernel thread scheduling, memory management, and RPC stacks to the ARM cores of Intel's Mount Evans Infrastructure Processing Unit (IPU). The engineering is careful and the results are honest: without Wave's PCIe latency mitigations, offloaded workloads degrade by 350%. We argue that this 350% degradation is not an engineering problem to be optimized away but a diagnostic symptom of a deeper architectural issue: Wave's communication model is Forward-In-Time-Only (FITO). Every interaction between host and SmartNIC is a unidirectional message -- event forward, decision back -- creating a temporal vulnerability window in which decisions can become stale before they are enforced. Wave's entire optimization stack (write-combining page table entries, prestaging, prefetching, atomic transaction abort) exists to hide or tolerate this window. We apply the FITO diagnostic to Wave's architecture systematically, identify the category mistake it inherits from Lamport's happened-before and Shannon's channel model, and show how Open Atomic Ethernet's bilateral swap primitive -- implemented on the same Intel IPU hardware -- dissolves the latency, atomicity, and timeout problems without engineering around them. The SmartNIC is the right location for resource management; what is missing is the right communication primitive at that location.

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