As Very Large Scale Integration (VLSI) designs continue to scale in size and complexity, layout verification has become a central challenge in modern Electronic Design Automation (EDA) workflows. In practice, congestion can only be accurately identified after detailed routing, making traditional verification both time-consuming and costly. Learning-based approaches have therefore been explored to enable early-stage congestion prediction and reduce routing iterations. However, although prior methods incorporate both netlist connectivity and layout features, they often model the two in a loosely coupled manner and primarily produce numerical congestion estimates. We propose VeriHGN, a verification framework built on an enhanced heterogeneous graph that unifies circuit components and spatial grids into a single relational representation, enabling more faithful modeling of the interaction between logical intent and physical realization. Experiments on industrial benchmarks, including ISPD2015, CircuitNet-N14, and CircuitNet-N28, demonstrate consistent improvements over state-of-the-art methods in prediction accuracy and correlation metrics.

翻译：随着超大规模集成电路（VLSI）设计在规模和复杂度上持续增长，版图验证已成为现代电子设计自动化（EDA）流程中的核心挑战。在实际中，拥塞问题只有在详细布线完成后才能被精确识别，这使得传统验证方法既耗时又昂贵。因此，基于学习的方法被探索用于实现早期拥塞预测并减少布线迭代次数。然而，尽管现有方法同时结合了网表连接性和版图特征，但它们通常以松散耦合的方式对两者进行建模，且主要生成数值化的拥塞估计。我们提出了VeriHGN，一个基于增强型异质图构建的验证框架，它将电路组件与空间网格统一到一个单一的关系表示中，从而能够更真实地建模逻辑意图与物理实现之间的相互作用。在包括ISPD2015、CircuitNet-N14和CircuitNet-N28在内的工业基准测试上的实验表明，该方法在预测精度和相关度量上均优于现有最先进方法。