Continual demand for memory bandwidth has made it worthwhile for memory vendors to reassess processing in memory (PIM), which enables higher bandwidth by placing compute units in/near-memory. As such, memory vendors have recently proposed commercially viable PIM designs. However, these proposals are largely driven by the needs of (a narrow set of) machine learning (ML) primitives. While such proposals are reasonable given the the growing importance of ML, as memory is a pervasive component, %in this work, we make there is a case for a more inclusive PIM design that can accelerate primitives across domains. In this work, we ascertain the capabilities of commercial PIM proposals to accelerate various primitives across domains. We first begin with outlining a set of characteristics, termed PIM-amenability-test, which aid in assessing if a given primitive is likely to be accelerated by PIM. Next, we apply this test to primitives under study to ascertain efficient data-placement and orchestration to map the primitives to underlying PIM architecture. We observe here that, even though primitives under study are largely PIM-amenable, existing commercial PIM proposals do not realize their performance potential for these primitives. To address this, we identify bottlenecks that arise in PIM execution and propose hardware and software optimizations which stand to broaden the acceleration reach of commercial PIM designs (improving average PIM speedups from 1.12x to 2.49x relative to a GPU baseline). Overall, while we believe emerging commercial PIM proposals add a necessary and complementary design point in the application acceleration space, hardware-software co-design is necessary to deliver their benefits broadly.

翻译：对内存带宽的持续需求促使存储器厂商重新评估存内处理（Processing-in-Memory，PIM）技术——该技术通过将计算单元置于内存内部或近内存位置，实现更高带宽。基于此，存储器厂商近期提出了若干具备商业可行性的PIM设计方案。然而，这些方案主要受（狭窄范畴的）机器学习基元的驱动。虽然鉴于机器学习日益增长的重要性，此类方案具有合理性，但作为无处不在的计算组件，内存需要更具包容性的PIM设计以跨领域加速各类基元。本文首先评估商用PIM设计方案加速跨领域基元的能力。我们提炼出一组称为"PIM适配性测试"的特征集，用于判定特定基元是否可能通过PIM获得加速。继而将该测试应用于待研究基元，通过优化数据放置与编排策略，将基元映射至底层PIM架构。研究发现：尽管所研究的基元大多具备PIM适配性，但现有商用PIM方案未能充分发挥其性能潜力。为此，我们识别PIM执行中的瓶颈，提出软硬件优化方案以拓展商用PIM设计的加速范围（相较于GPU基线，平均PIM加速比从1.12倍提升至2.49倍）。总体而言，我们认为新兴商用PIM方案在应用加速领域提供了必要且互补的设计维度，但需通过软硬件协同设计才能广泛释放其性能优势。