It has been shown that unclocked, recurrent networks of Boolean gates in FPGAs can be used for low-SWaP reservoir computing. In such systems, topology and node functionality of the network are randomly initialized. To create a network that solves a task, weights are applied to output nodes and learning is achieved by adjusting those weights with conventional machine learning methods. However, performance is often limited compared to networks where all parameters are learned. Herein, we explore an alternative learning approach for unclocked, recurrent networks in FPGAs. We use evolutionary computation to evolve the Boolean functions of network nodes. In one type of implementation the output nodes are used directly to perform a task and all learning is via evolution of the network's node functions. In a second type of implementation a back-end classifier is used as in traditional reservoir computing. In that case, both evolution of node functions and adjustment of output node weights contribute to learning. We demonstrate the practicality of node function evolution, obtaining an accuracy improvement of ~30% on an image classification task while processing at a rate of over three million samples per second. We additionally demonstrate evolvability of network memory and dynamic output signals.

翻译：已有研究表明，现场可编程门阵列（FPGA）中的无时钟循环布尔门网络可用于低SWaP（尺寸、重量与功耗）储层计算。此类系统中，网络的拓扑结构与节点功能随机初始化。为解决特定任务，对输出节点施加权重，并通过传统机器学习方法调整权重实现学习。然而，与全参数学习网络相比，其性能常受局限。本文探索了FPGA中无时钟循环网络的替代学习方法：采用演化计算演化网络节点的布尔函数。第一种实现方式中，输出节点直接用于执行任务，所有学习均通过网络节点功能演化完成；第二种实现方式则沿用传统储层计算的后续分类器。此时，节点功能演化与输出节点权重调整共同促成学习。我们验证了节点功能演化的实用性：在图像分类任务中，以每秒超过三百万个样本的处理速率实现约30%的精度提升。此外，还展示了网络记忆与动态输出信号的可演化性。