Due to the unavailability of routing information in design stages prior to detailed routing (DR), the tasks of timing prediction and optimization pose major challenges. Inaccurate timing prediction wastes design effort, hurts circuit performance, and may lead to design failure. This work focuses on timing prediction after clock tree synthesis and placement legalization, which is the earliest opportunity to time and optimize a "complete" netlist. The paper first documents that having "oracle knowledge" of the final post-DR parasitics enables post-global routing (GR) optimization to produce improved final timing outcomes. To bridge the gap between GR-based parasitic and timing estimation and post-DR results during post-GR optimization, machine learning (ML)-based models are proposed, including the use of features for macro blockages for accurate predictions for designs with macros. Based on a set of experimental evaluations, it is demonstrated that these models show higher accuracy than GR-based timing estimation. When used during post-GR optimization, the ML-based models show demonstrable improvements in post-DR circuit performance. The methodology is applied to two different tool flows - OpenROAD and a commercial tool flow - and results on 45nm bulk and 12nm FinFET enablements show improvements in post-DR slack metrics without increasing congestion. The models are demonstrated to be generalizable to designs generated under different clock period constraints and are robust to training data with small levels of noise.

翻译：由于在详细布线（DR）之前的设计阶段无法获得布线信息，时序预测与优化任务面临着重大挑战。不准确的时序预测会浪费设计精力、损害电路性能，甚至可能导致设计失败。本研究聚焦于时钟树综合与布局合法化之后的时序预测，这是能够对“完整”网表进行时序分析与优化的最早时机。论文首先证明，若拥有最终DR后寄生参数的“先验知识”，则可在全局布线（GR）后优化中取得更优的最终时序结果。为弥合GR寄生参数及时序估算与DR后结果之间的差距，本文提出了基于机器学习（ML）的模型，包括利用宏模块阻塞特征对含宏模块的设计进行精确预测。通过一系列实验评估，这些模型在精度上优于基于GR的时序估计。在GR后优化中使用这些ML模型时，能显著提升DR后的电路性能。该方法已应用于两种不同的工具流程——OpenROAD与商业工具流程，针对45nm体硅工艺与12nm FinFET工艺的实验结果表明，DR后的时序松弛指标得到改善且未增加拥塞。实验验证表明，这些模型可推广至不同时钟周期约束下生成的设计，并对含小幅噪声的训练数据具有鲁棒性。